Development efforts are being made for increasing the number of memory cells fabricated on a single semiconductor chip. However, the more memory cells we integrate on a single semiconductor chip, the less yield we suffer in production. One of the approaches to enhance the production yield is to provide a redundant memory cells which are replaced with defective memory cells in the major memory cell array.
In one prior-art semiconductor memory device, the redundant memory cells are arranged in rows, and each row of the redundant memory cells are accompanied by a redundant word line. If a defective memory cell is detected in the major memory cell array during the diagnostic operation, all of the memory cells coupled to the word line together with the defective memory cell are replaced with the redundant memory cells coupled to the redundant word line. Another prior-art semiconductor memory device is provided with a redundant memory cell array arranged in columns, and each column of the redundant memory cells are coupled to a redundant bit line. However, a problem is encountered in these prior-art semiconductor memory devices in limitation of the defective memory cells rescued by the replacement with the redundant memory cells. This is because of the fact that the word line or the bit line coupled to the defective memory cell is in its entirety replaced with the redundant word line or the redundant bit line.
In order to increase the relievable detected memory cells, there is proposed a semiconductor memory device provided with a redundant memory cell array accompanied by both the redundant word lines and the redundant bit lines. However, another problem is encountered in the semiconductor memory device in complexity in arrangement of the switching circuit operative to change the defective memory cell to the replaced redundant memory cell. This complexity results in a delay in transmission of the data bit read out from the redundant memory cell.
One of the solutions is proposed to overcome the problem inherent in the above semiconductor memory device provided with the redundant memory cell array accompanied by both the redundant word lines and the redundant bit lines. The solution is disclosed in, for example, Japanese patent Publication (Kokoku) No. 62-21198. The semiconductor memory device disclosed in the Japanese Patent Publication is illustrated in FIG. 1 of the drawings and comprises a major memory cell array 1 having a plurality of major memory cells arranged in rows and columns, an X decoder circuit 2, a first Y decoder circuit 3, a group of write-in/sense amplifier circuits 4, 5, 6, 7, 8, 9, 10 and 11, a multiplexer 12 and a second Y decoder circuit 13. The major memory cell array 1 is divided into a plurality of major memory cell blocks 14, 15, 16, 17, 18, 19, 20 and 21 each of which is associated with each write-in/sense amplifier circuit 4, 5, 6, 7, 8, 9, 10 or 11. The semiconductor memory device further comprises a redundant memory cell block 22 and an additional write-in/sense amplifier circuit 23 dedicated to the redundant memory cell block 22, and one of the major memory cell blocks is replacable with the redundant memory cell block 22 if defective memory cells are incorporated in the major memory cell block. This means that the redundant memory cell block 22 should be designed to be identical in size with each major memory cell block.
Upon reading-out operation, a data bit is supplied from each of the major memory cell blocks 14 to 21 to each of the write-in/sense amplifier circuits 4 to 11 in accordance with selections executed by the X decoder circuit 2 and the first Y decoder circuit 3. The X decoder circuit 2 and the first Y decoder circuit 3 also supply the redundant memory cell block 22 with the selecting signals, so that a data bit is read out from the redundant memory cell block 22 and, then, transferred to the write-in/sense amplifier circuit 23. With the selecting signal produced by the second Y decoder circuit 13, one of the data bits fed from the write-in/sense amplifier circuits 4 to 11 is transmitted to an output node. However, if one of the major memory cell block is replaced with the redundant memory cell block 22, the multiplexer 12 transmits the data bit fed from the write-in/sense amplifier circuit 23 to the output node 24 instead of the data bit read out from the major memory cell block incorporating the defective memory cell or cells. Thus, the second Y decoder circuit 23 participates in the alternation of the write-in/sense amplifier circuit. The second Y decoder circuit 13 is relatively simple in circuit arrangement in comparison with the switching circuit described above, so that a negligible amount of delay takes place upon transmission of the data bit.
However, the prior-art semiconductor memory device shown in FIG. 2 has a problem in a large amount of occupation area. Namely, the defective major memory cell block merely has a bit line or some bit lines necessary to be replaced, so that a smaller major memory cell block is preferable for reduction of unusable major memory cells. However, each major memory cell block is accompanied by the write-in/sense amplifier circuit dedicated thereto, so that increasing the number of the major memory cell blocks results in increasing the number of the write-in/sense amplifier circuits. This means that there is a serious trade-off between the number of unusable major memory cells and the number of write-in/sense amplifier circuits. Thus, the semiconductor memory device shown in FIG. 1 consumes a large amount of area on the semiconductor chip.